Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. We bring passion and dedication to our job and there's no telling what we could accomplish. Smart people and inspiring, innovative technologies are the norm here. Do you love working on challenges that no one has solved yet? Are you ready to be part of a team transforming technology? Join us to help deliver the next groundbreaking Apple product. In this role, you will be a key member of our team in Munich, acting as backend focal point for all timing and constraints development, working in advanced technologies and directly collaborating closely both with RTL designers and Physical Designers, towards completion of Analog Mixed Signal IPs.

Description
As a Static Timing Engineer, you will be spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will also closely collaborate with RTL designers to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical Design team to close and sign-off timing. You will come up with ideas and plans to verify your own timing constraints, innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fallouts in timing analysis.

Preferred Qualifications
Bachelor or Master’s degree in Electrical Engineering or relevant years of experience.

Apple is an Equal Opportunity Employer committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

Minimum Qualifications
We look forward to hearing your detailed knowledge of the ASIC design timing closure flow and methodology, as this role requires. Ideally you will have:

Relevant years of experiences in writing ASIC timing constraints and timing closure.
Validated experiences in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations & signal integrity related issues.
Hands on experiences in timing/SDC constraints generation and management.
Proficient in scripting languages (Tcl and Perl).
Have good knowledge in synthesis, DFT and backend related methodology and tools.
Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams.
Ability to work well in an international team, take responsibility, perform under strict deadlines and motivate self to balance priorities.
Proficiency in English language is required